IC Layout Engineer

We are looking for a IC Layout Engineer with experience in GPIO and I/O cell design to join our growing team. You will be responsible for the physical layout implementation of GPIO blocks, ensuring compliance with design rules, reliability standards, and integration into top-level chip designs.

Key Responsibilities

• Perform layout design for GPIO and other I/O-related circuits based on schematics and design guidelines.
• Handle floorplanning, device placement, and routing of transistors, pads, ESD structures, and guard rings.
• Ensure DRC, LVS, and ERC compliance.
• Implement ESD protection and follow latch-up prevention measures.
• Collaborate with circuit design engineers to meet performance, timing, and reliability requirements.
• Support parasitic extraction (PEX) and assist in post-layout simulation.
• Contribute to top-level pad ring integration and interface with multiple power domains.
• Participate in continuous improvement for layout methodologies and automation flows.

Qualifications

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, or related field.
• Atleast 2 years of experience in IC layout engineering, with exposure to GPIO or I/O cells.
• Strong knowledge of physical verification (DRC, LVS, ERC) and parasitic extraction.
• Familiarity with ESD protection techniques, latch-up prevention, and reliability checks.
• Hands-on experience with industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Validator).
• Strong problem-solving skills, attention to detail, and ability to work in a collaborative environment.